BANGALORE, India, Nov. 6, 2019 /CNW/ -- Valtrix Systems, provider of design verification products for building functionally correct CPU and system-on-chip implementations, will have a visible presence at the upcoming RISC-V Summit taking place in San Jose Convention Center, San Jose, California from 10-12 December.
Valtrix will highlight its flagship product – STING, the industry's first commercial RISC-V verification solution, at exhibition booth #302. Of note will be STING's Test Stimulus Programming Framework which can be utilized by users to exercise custom RISC-V extensions or underlying micro-architectural implementation. Also featured will be the STING based RISC-V architecture verification suite, a comprehensive collection of self-checking test cases identified in a verification plan derived from the RISC-V user and privilege level specifications.
Managing Director Shubhodeep Roy Choudhury will also be presenting a session on 'Verifying RISC-V Vector and Bit Manipulation Extensions using STING Design Verification Tool' during the RISC-V Summit on Wednesday, December 11.
Attendees can arrange meetings to discuss about STING and its support for RISC-V implementations by writing to [email protected]
Valtrix Systems is an EDA startup delivering products and solutions for design verification of SoC/IP/CPU implementations. Formed with a mission of creating world class tools and testing methodologies that will help companies efficiently verify the designs of IPs and SoCs, Valtrix partners with a number of RISC-V vendors to verify their products faster and more cost-effectively. Its flagship product, STING design verification tool embodies constrained random, directed and graph-based test generation methodologies and is well-suited for verification of a wide variety of RISC-V implementations ranging from IoT/embedded to server platforms. Visit www.valtrix.in to learn more.
Connect with Valtrix at:
Shubhodeep Roy Choudhury
SOURCE Valtrix Technologies Private Limited