New TSMC Reference Flow 9.0 Supports 40nm Process Technology

    Continued improvements in low power design, statistical design, and DFM

    HSINCHU, Taiwan, June 3 /CNW/ -- Taiwan Semiconductor Manufacturing
Company, Ltd. (TSE: 2330, NYSE:   TSM) today introduced Reference Flow 9.0, the
latest version of TSMC's industry-leading design methodology to lower design
obstacles, improve design margins, and increase yields of its 40nm process
technology. Reference Flow 9.0 is also one of the key collaborative components
of the company's recently unveiled Open Innovation Platform(TM).
    Hosted by TSMC, the Open Innovation Platform is available only to
customers and ecosystem partners to improve time-to-market, increase return on
investment, and reduce waste. The Open Innovation Platform is built on TSMC's
design-enabling building blocks and an ecosystem interface.
    Reference Flow 9.0 addresses new design challenges of TSMC's advanced
technologies up to and including 40nm process technology, with features such
as transparent half-node design, support for new low power automation flow via
Unified Power Format (UPF) in addition to Common Power Format (CPF) enabled
flow, new statistical design features, and hierarchical DFM capability.
    The TSMC Open Innovation Platform(TM) promotes the speedy implementation
of innovation amongst the semiconductor design community, its ecosystem
partners and TSMC's IP, design implementation and DFM capabilities, process
technology and backend services. A key element of the Open Innovation
Platform(TM) is a set of ecosystem interfaces and collaborative components
initiated and supported by TSMC that more efficiently empowers innovation
throughout the supply chain and which enables the creation and sharing of
newly created revenue and profitability. TSMC's Active Accuracy Assurance(TM)
(AAA) initiative is a critical part of the Open Innovation Platform(TM),
providing the accuracy and quality required by the ecosystem interfaces and
collaborative components.
    Reference Flow 9.0 is supported by the same AAA initiative that defines
standards of accuracy for all of TSMC's design ecosystem partners. Reference
Flow 9.0 focuses on ease-of-use and provides a reference of qualified design
tools and flows that give designers a proven path from specification to
    "A number of TSMC customers have started their next-generation chip
designs in our latest 40nm process technology and require a reference design
methodology," said S.T. Juang, senior director of design infrastructure
marketing at TSMC. "Reference Flow 9.0 is the result of our early and deep
collaboration with EDA vendors and other design ecosystem partners. The result
is a production-proven design infrastructure that allows designers to take
full advantage of our most advanced process technologies."
    Advanced Low-Power Design
    Reference Flow 9.0 includes a number of innovative power reduction
techniques including TSMC's advanced clock gating design flow for dynamic
power reduction. The new low-power clock tree synthesis supports
multi-mode/multi-corner, and on-chip variation to reduce active and leakage
power. Reference Flow 9.0 supports both the CPF and UPF. Additional validation
has been carried out on the interoperability of the low power solutions
provided by the UPF members. Together these features reduce chip power
consumption, extend battery life for portable devices, and reduce system
packaging and cooling costs.
    Transparent Half-Node Design Support
    Reference Flow 9.0 delivers transparent half-node designs, eliminating
the need for designers to define the half-node scaling factor multiple times
in different tools throughout whole design cycle in order to migrate a design
from a full node to a "shrink" node by traditional design flows. Designers can
use Reference Flow 9.0 to start chip design using 45nm rules, and
transparently target the design toward 40nm without explicitly dealing with a
multitude of scaling factors.
    Enhanced Timing and Statistical Design
    Reference Flow 8.0 introduced the first foundry design methodology to
include intra-die statistical timing analysis along with statistical leakage
and statistical timing optimization. To further improve setup and hold timing
margins, Reference Flow 9.0 now supports stage-based on-chip variation, as
well as design-specific on-chip variation derived from statistical analysis.
In addition, new transistor-level path-based statistical static timing
analysis (SSTA) is introduced to enhance timing accuracy and reduce the need
for pre-characterized cell libraries. These features enable designers to
reduce excess design margins, optimize design performance and increase yields.
    Design for Manufacturability (DFM)
    Reference Flow 9.0 provides significant improvements in both physical and
electrical DFM capabilities to speed up DFM analysis for large designs and
address potential parametric performance shifts caused by DFM effects.
Reference Flow 9.0 offers hierarchical DFM analysis for all three physical DFM
effects: LPC, CMP and CAA, significantly reducing design iterations,
accelerating DFM analysis, and improving accuracy when DFM information is
annotated to the design abstracts.
    Electrical DFM improvements include table-based DFM-LPE extraction flow
for faster extraction turnaround, while maintaining the accuracy of the model-
based DFM approach. Shape-to-Electrical (S2E) and Thickness-to-Electrical
(T2E) DFM engines are now silicon-based models, which improves the accuracy of
the predicted electrical performance of the design. Hierarchical analysis
capability and more accurate DFM models shorten design cycles by enabling
designers to anticipate DFM issues and take necessary measures to improve
design robustness and increase yields.
    About TSMC
    TSMC is the world's largest dedicated semiconductor foundry, providing
the industry's leading process technology and the foundry industry's largest
portfolio of process-proven libraries, IP, design tools and reference flows.
The Company's total managed capacity in 2007 exceeded eight million (8-inch
equivalent) wafers, including capacity from two advanced 12-inch Gigafabs,
four eight-inch fabs, one six-inch fab, as well as TSMC's wholly owned
subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC.
TSMC is the first foundry to provide 40nm production capabilities. Its
corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC
please see

For further information:

For further information: Chuck Byers of TSMC, +1-408-382-7919 Web Site:

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