Risk production expected in Q3 2010
HSINCHU, Taiwan, R.O.C., Aug. 24 /CNW/ -- Taiwan Semiconductor
Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) today announced that it is
adding a low power process to its 28nm high-k metal gate (HKMG) road map. The
new process is expected to enter risk production in the third quarter of 2010.
TSMC's 28nm development and ramp has remained on schedule since the
company announced the technology in September 2008. The new process' risk
production follows the HKMG high performance (HP) process by one quarter and
the low power (LP) silicon oxynitride (SiON) process by two quarters. Risk
production for the 28nm low power (LP) SiON process is scheduled for the end
of first quarter of 2010, while risk production for the 28nm HP process is
expected at the end of second quarter, 2010.
The 28nm HPL (low power with HKMG) process is a derivative of TSMC's high
performance HKMG technology and features low power, low leakage, and
medium-high performance on a gate-last approach. It supports low leakage
applications such as cell phone, smart netbook, wireless communication and
portable consumer electronics.
The 28nm HPL process comes complete with comprehensive device support and
is considered suitable as a SoC platform for general market applications. It
is differentiated from the 28LP technology, which is positioned for cellular
and handheld applications where lower cost and faster time-to-market from an
evolutionary SiON process is most attractive.
The 28nm HP process, announced as part of the September 2008
introduction, is also built on a gate-last approach and supports performance
driven devices such as CPUs, GPUs, Chipsets, FPGAs, video game console and
mobile computing applications.
"We developed a gate-last approach for TSMC's 28nm high-k metal gate
family that is superior in terms of transistor characteristics, high end and
low end performance upside, and manufacturability," said Dr. Jack Sun, vice
president, Research and Development, TSMC.
"TSMC has been working with customers over a significant period of time
to develop high-k metal gate technologies for low power applications. The
addition of the 28nm HPL to the 28nm technology family, combined with the 28LP
and 28HP, means that TSMC now provides the most comprehensive 28nm technology
portfolio," said Dr. Mark Liu, senior vice president, Advanced Technology
To fully utilize the power of the 28nm technology family for a broad
range of differentiating products, TSMC is working closely with customers and
ecosystem partners to build a comprehensive design infrastructure based on the
company's recently unveiled Open Innovation Platform(TM). The Open Innovation
Platform(TM), hosted by TSMC, is open to TSMC customers and partners.
TSMC is the world's largest dedicated semiconductor foundry, providing
the industry's leading process technology and the foundry's largest portfolio
of process-proven libraries, IP, design tools and reference flows. The
Company's total managed capacity in 2008 exceeded 9 million 8-inch equivalent
wafers, including capacity from two advanced 12-inch - GigaFabs(TM), four
eight-inch fabs, one six-inch fab, as well as TSMC's wholly owned
subsidiaries, WaferTech and TSMC (China), and its joint venture fab, SSMC.
TSMC is the first foundry to provide 40nm production capabilities. Its
corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC
please visit http://www.tsmc.com.
For further information:
For further information: Wendy Matthews, North America, +1-408-382-8030,
or Michael Kramer, Corporate Public Relations, 886-3-5636688 ext. 7126216,
both of TSMC Web Site: www.tsmc.com